Writing

Memory Design 101

A series on SRAM fundamentals: how a cell stores data, read and write behaviour, voltage limits, and failure mechanisms.

1. What does a memory cell actually store?
2. Why is writing harder than reading?
3. What actually sets SRAM Vmin?
4. Why read Vmin and write Vmin fail for different reasons
5. Three different read failures people call “read disturb”

Interconnects

Posts on wire delay, conductor materials, dielectrics, metal layers, and vias.

• Why wires limit chip speed
• Copper and ruthenium interconnects
• Low-k dielectrics and air gaps
• Why upper metal wires get bigger
• Via resistance at advanced nodes

Articles

More semiconductor posts

• Temperature inversion and timing
• SRAM PUFs: using process variation for security
• On-chip SRAM bottlenecks in AI systems
• LLM quantization, BitNet, and low-bit computing
• Moore’s law: from transistor scaling to system design
• CPU clock speeds and Dennard scaling
• How Apollo 11’s computer helped land on the Moon