Publications

Research in energy-efficient AI hardware: approximate arithmetic, posit-based accelerators, memory architecture, and in-memory computing.

My research addresses both computation and memory in AI hardware, from approximate arithmetic and posit-based accelerators to SRAM circuits and in-memory computing. Explore the research themes and projects.

24 publications shown

2025Conference

VeriBench: Benchmarking Large Language Models for Verilog Code Generation and Design Synthesis

Mihir Agarwal, Zaqi Momin, Kailash Prasad, and Joycee Mekie

IEEE International Symposium on Circuits and Systems (ISCAS), 2025, pp. 1–5

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2025Conference

Robust and High-Performance Digital In-Memory Computing in 5T Gain Cell Embedded DRAM

Kailash Prasad, Rajat Borkar, and Joycee Mekie

VLSI Design and Test (VDAT) 2023; proceedings: VLSI for Embedded Intelligence, Lecture Notes in Electrical Engineering, vol. 1210, pp. 63–76. Springer citation year: 2025; first online: 28 October 2024

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2024Conference

SDR-PUF: Sequence-Dependent Reconfigurable SRAM PUF with an Exponential CRP Space

Kailash Prasad, Neel Shah, Jinay Dagli, and Joycee Mekie

37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems (VLSID), 2024, pp. 535–540

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2024Conference

Hybrid CMOS-Memristor Logic for Boosting the Power-Efficiency in Error Tolerant Applications

Monika Pokharia, Kailash Prasad, Ravi S. Hegde, and Joycee Mekie

37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems (VLSID), 2024, pp. 431–436

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2024Conference

FP-BMAC: Efficient Approximate Floating-Point Bit-Parallel MAC Processor using IMC

Saketh Gajawada, Aryan Gupta, Kailash Prasad, and Joycee Mekie

37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems (VLSID), 2024, pp. 241–246

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2024Conference

FP-ATM: A Flexible Floating Point NOR Adder Tree Macro for In-Memory Computing

Yathin Kumar Attuluri, Ruchit Chudasama, Kailash Prasad, and Joycee Mekie

37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems (VLSID), 2024, pp. 247–252

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2023Conference

PVC-RAM: Process Variation Aware Charge Domain In-Memory Computing 6T-SRAM for DNNs

S. Shubham, S. Pandit, K. Prasad, and J. Mekie

Design Automation Conference (DAC) 2023

Publications

VeriBench: Benchmarking Large Language Models for Verilog Code Generation and Design Synthesis

Robust and High-Performance Digital In-Memory Computing in 5T Gain Cell Embedded DRAM

SDR-PUF: Sequence-Dependent Reconfigurable SRAM PUF with an Exponential CRP Space

Hybrid CMOS-Memristor Logic for Boosting the Power-Efficiency in Error Tolerant Applications

FP-BMAC: Efficient Approximate Floating-Point Bit-Parallel MAC Processor using IMC

FP-ATM: A Flexible Floating Point NOR Adder Tree Macro for In-Memory Computing

PVC-RAM: Process Variation Aware Charge Domain In-Memory Computing 6T-SRAM for DNNs

Process Variation Resilient Current-Domain Analog In Memory Computing

PIC-RAM: Process-Invariant Capacitive Multiplier Based Analog In Memory Computing in 6T SRAM

Hardware-Software Codesign of DNN Accelerators using Approximate Posit Multipliers

Fast and Robust Sense Amplifier Design for Digital IMC

Impact of approximation and commutativity on Neural Network and Image Processing Applications

An Automated Approach to Compare Bit Serial and Bit Parallel In-Memory Computing for DNN

FastMem: A Fast Architecture-aware Memory Layout Design

Analysis of Word Line Shaping Techniques for In-Memory Computing in SRAMs

SEDAAF: FPGA Based Single Exact Dual Approximate Adders for Approximate Processors

FPAD: a Multistage Approximation Methodology for Designing Floating Point Approximate Dividers

HyGain: High Performance, Energy-Efficient Hybrid Gain Cell-based Cache Hierarchy

Energy Efficient Domain-Specific Hardware Design

WA-PUF: A Highly Random Write-Assist Based Sequence-Dependent SRAM-based PUF

Energy Efficient Domain-Specific Hardware Design

Linear Column Major Capacitive multiplier based Analog In-Memory Computing Architecture

IMC-Enabled SRAM PUF based on Bitline Computing and Write-back

Analysis of Word Line Shaping Techniques for In-Memory Computing in SRAMs