SRAM design
At Arm, I work on SRAM circuit design and characterization at advanced technology nodes. My work includes circuit sizing, timing and power analysis, and checking read and write margins across process, voltage, and temperature conditions.
I work on SRAM circuit design and characterization at Arm in Noida. I completed my Ph.D. in Electrical Engineering at IIT Gandhinagar under Prof. Joycee Mekie, where my research focused on in-memory computing and approximate computing.
Alongside my engineering work, I write about semiconductors and share learning resources for students interested in VLSI.

At Arm, I work on SRAM circuit design and characterization at advanced technology nodes. My work includes circuit sizing, timing and power analysis, and checking read and write margins across process, voltage, and temperature conditions.
My doctoral research explored analog and digital computation within SRAM and gain-cell memories. I also worked on approximate arithmetic and posit-based hardware for neural-network accelerators.
I have taught IC design, supported NPTEL courses, and mentored students on VLSI projects. I also write about memory design and semiconductors on LinkedIn, using circuit examples to explain the ideas.
A capacitive multiplier for analog in-memory computing in 6T SRAM, designed to reduce the effect of process variation on multiplication.
A current-domain approach to analog in-memory computing that addresses the effect of process variation on computation accuracy.
Approximate posit multipliers and DNN accelerator design, studying the trade-off between numerical accuracy and hardware cost.
I spoke with students about VLSI career paths and how circuit design, timing, and engineering decisions connect academic learning with industry work.
Event detailsA talk about my path from doctoral circuit research at IIT Gandhinagar to memory design at Arm.
Event programmeA conversation about starting a Ph.D. after B.Tech., research at IIT Gandhinagar, the PMRF fellowship, and VLSI career paths.
Watch on YouTubeHow does a memory cell store data? Why is writing harder than reading? What sets SRAM Vmin? I explore these questions through circuit examples.
Read the seriesI grew up in Arunachal Pradesh and studied Electronics and Communication Engineering at NIT Arunachal Pradesh before joining IIT Gandhinagar for my Ph.D.
At IIT Gandhinagar, I worked with Prof. Joycee Mekie in the nanoDC Lab on in-memory computing and approximate computing. My doctoral work included circuit research, two UMC 65 nm tapeouts, and teaching IC design.
I joined Arm in Noida in October 2023 and defended my Ph.D. in June 2024. I now work on SRAM design and characterization, while continuing to write about semiconductors and mentor students.
View my CVSenior Design Engineer, Physical IP Group.
SRAM circuit design and characterization at advanced technology nodes.
Electrical Engineering, nanoDC Lab.
Advisor: Prof. Joycee Mekie. Research in in-memory computing and approximate computing.
Worked with a student team on the design and implementation of memory and computing circuits for two chip tapeouts.
Electronics and Communication Engineering.
Chairman Gold Medal and Institute Gold Medal.
At IIT Gandhinagar, I taught the Digital IC Design Lab as a Graduate Teaching Fellow and supported other courses as a teaching assistant. I also worked as a tutor for NPTEL’s Digital Circuits and Design and Analysis of VLSI Subsystems courses.
I share presentations, programming tutorials, and recorded tutorial sessions. Each resource lists my contribution, collaborators, and course instructors.
All learning resourcesDuring my Ph.D., I received the Prime Minister’s Research Fellowship and Intel India Research Fellowship in 2020. I was also an SRC Research Scholar.
I received IIT Gandhinagar’s Outstanding Graduate Teaching Fellow Award in 2022 for my work teaching the IC Design course.
I served as Track Co-Chair for ULSI Circuits, System-on-Chip, and Power SoC at ICEE 2025. I also review research papers and collaborate with students and researchers.
CollaboratorsLet's connect
For research discussions, invited talks, or conversations about memory design and VLSI education.