I am Kailash Prasad, a Prime Minister Research Fellow at the Indian Institute of Technology Gandhinagar. I completed my B.Tech. in Electronics and Communication Engineering from the National Institute of Technology Arunachal Pradesh in 2018, and I was awarded Chairman and Institute Gold Medal for outstanding academic performance. Currently, I am pursuing Ph.D. in Electrical Engineering at the nanoDC Lab, IIT Gandhinagar, under the guidance of Prof. Joycee Mekie.
My research focuses on hardware for machine learning, in-memory computing, approximate computing, CAD tool design, and SRAM memory subsystem design. I am an SRC Research Scholar and the recipient of the Intel India Research Fellowship in 2020. My work has been accepted and recognized in premier EDA conferences such as ASP-DAC and DATE, with some papers receiving Best Paper Nominations. I also serve as a reviewer for various conferences, including ISCAS, AICAS, and journals such as IEEE TCAS I and TCAS II.
I expertise in RTL to GDS flow for digital IC design, and I have had the opportunity to lead a team of 15 people for two tapeouts in UMC 65nm in 2020 and 2022. Additionally, I expertise in SRAM memory subsystem design for digital and analog in-memory computing and physical unclonable function.
I am passionate about designing circuits, teaching microelectronics and VLSI, and building an army of VLSI engineers. During my tenure of Ph.D, I have been fortunate to have the opportunity to build and lead teams, which has been an enriching experience.
My belief in the importance of perseverance and determination can be summarized with this quote:
"Overcoming barriers may require us to take different paths - sometimes we cross over, sometimes we tunnel through, and sometimes we break them down altogether. But with determination and a willingness to explore new avenues, we can always reach our destination." - KP
News and Highlights
|Awarded ACM SIGDA and IEEE CEDA travel grant from DAC to attend DAC 2023
|PhD thesis extended abstract has been accepted to Design Automation Conference DAC'23 PhD Forum.
|Paper Titled "PVC-RAM: Process Variation Aware Charge Domain In-Memory Computing 6T-SRAM for DNNs" has been accepted to Design Automation Conference DAC 2023
|WiP Poster Titled "WA-PUF: Write-Assist Augmentation of Sequence Dependent SRAM PUF for Enhanced Randomness and Uniqueness" has been accepted to Design Automation Conference DAC 2023
|Awarded travel grant from DATE to attend DATE 2023
|Paper Titled "Process Variation Resilient Current-Domain Analog In Memory Computing" has been accepted to Design Automation and Test in Europe Conference DATE 2023.
|PhD thesis extended abstract has been accepted to Design Automation and Test in Europe Conference DATE'23 PhD Forum.
|Paper Titled "HyGain: High Performance, Energy-Efficient Hybrid Gain Cell based Cache Hierarchy" has been selected to appear in the Association for Computing Machinery (ACM) Showcase on Kudos.
|Paper Titled "PIC-RAM: Process-Invariant Capacitive Multiplier Based Analog In Memory Computing in 6T SRAM" has been accepted to Design Automation and Test in Europe Conference DATE 2023. It has also been nominated for Best Paper Award.
|Paper Titled "Hardware-Software Codesign of DNN Accelerators using Approximate Posit Multipliers" to be presented at ASP-DAC 2023 has been nominated for Best Paper Award.
|Proposal Titled "Fast and Efficient ML Hardware Accelerator Designs for SoCs with integrated FPGA" has been accepted to VLSID Design Contest 2023
|Received Outstanding Graduate Teaching Fellow Award for Teaching IC Design Course
|1 paper accepted at International VLSI Design & Embedded Systems Conference VLSID 2023
|1 paper accepted at Asia and South Pacific Design Automation Conference ASP-DAC 2023
|1 paper accepted at ACM Transactions on Architecture and Code Optimization TACO 2022
|1 paper accepted at International Symposium on VLSI Design and Test VDAT 2022
|Selected for DAC Young Fellow Program - DAC 2022
|2 works accepted for Poster Presentation at Design Automation Conference DAC 2022
|Graduate Teaching Fellow (Instructor) for IC Design Lab at IIT Gandhinagar
|1 paper accepted at IEEE International Symposium on Circuits and Systems ISCAS 2022
|1 paper accepted at IEEE International Symposium on Quality Electronic Design ISQED 2022
|Best Research Video Award at the DAC 2021 Young Fellows Program - Link to the video
|Selected for DAC Young Fellow Program - DAC 2021
|1 paper accepted at IEEE International Conference on Electronics Circuits and Systems ICECS 2021
|Awarded the Prestigious Prime Minister's Research Fellowship (PMRF) 2020
|Awarded the Prestigious Intel India Research Fellowship 2020
|Learn Python Programming during this COVID 19 Pandemic. Click Here
|2 papers accepted at IEEE International Symposium on Circuits and Systems ISCAS 2020
|Awarded travel grant from VLSID to attend VLSID 2020
|Awarded travel grant from ACM SIGARCH to attend ISCA 2019 and uArch Workshop
- Memory Centric Circuits and Architectures
- Approximate Circuits and Architectures for Machine Learning
- Hardware Design for Posit Number System
- AI Based Hardware Design
- SRAM Peripherals and Memory Subsystem Design
- Ph.D in Electrical Engineering, IIT Gandhinagar, 2018 - Present
- B.Tech in Electronics and Communication Engineering, NIT Arunachal Pradesh, 2018
Teaching and Research Experience
|Jan 23 - Apr 23
|IIT Madras (NPTEL)
|Prof. Madhav Rao
|Course : Design and analysis of VLSI Subsystem - Youtube Playlist
|Jul 22 - Oct 22
|IIT Kharagpur (NPTEL)
|Prof. Santanu Chattopadhyay
|Course : Digital Circuits - Youtube Playlist
|Jan 22 - Apr 22
|Graduate Teaching Fellow
|Prof. Joycee Mekie
|Course : IC Design Lab
|Aug 18 - Present
|Prof. Joycee Mekie
|Course : Digital System, Embedded System, Microelectronics Lab, Computer Organisation and Architecture, VLSI Design, IC Design
|May 17 - July 17
|Student Research Associate
|Prof. Yogesh Singh Chauhan
|Topic : Compact Modelling and TCAD simulation of semiconductor devices.