KP.Kailash Prasad
SRAM circuit design · Arm, Noida

Kailash Prasad

I work on SRAM circuit design and characterization at Arm in Noida. I completed my Ph.D. in Electrical Engineering at IIT Gandhinagar under Prof. Joycee Mekie, where my research focused on in-memory computing and approximate computing.

Alongside my engineering work, I write about semiconductors and share learning resources for students interested in VLSI.

ProjectsPublications
Kailash Prasad
Kailash PrasadSenior Design Engineer · Arm, Noida
Across industry
and academiaArmMemory designIIT GandhinagarPh.D. · Electrical EngineeringPMRFResearch fellowshipIntelIndia Research Fellowship

Work and research interests

Tools & expertise

SRAM design

At Arm, I work on SRAM circuit design and characterization at advanced technology nodes. My work includes circuit sizing, timing and power analysis, and checking read and write margins across process, voltage, and temperature conditions.

SRAMCircuit designCharacterization

In-memory computing

My doctoral research explored analog and digital computation within SRAM and gain-cell memories. I also worked on approximate arithmetic and posit-based hardware for neural-network accelerators.

In-memory computingApproximate computingHardware–software codesign

Teaching and technical writing

I have taught IC design, supported NPTEL courses, and mentored students on VLSI projects. I also write about memory design and semiconductors on LinkedIn, using circuit examples to explain the ideas.

TeachingMentoringTechnical writing

Selected research

All publications
DATE 2023Best Paper Candidate

PIC-RAM

A capacitive multiplier for analog in-memory computing in 6T SRAM, designed to reduce the effect of process variation on multiplication.

6T SRAMAnalog in-memory computing
View publication
DATE 2023

Process Variation Resilient Current-Domain Analog In Memory Computing

Process variation can affect the accuracy of analog computation. This work studies a current-domain in-memory computing approach designed to make computation more resilient to those variations.

View publication
ASP-DAC 2023

Hardware-Software Codesign of DNN Accelerators using Approximate Posit Multipliers

This work combines approximate posit multipliers with DNN accelerator design, studying the trade-off between numerical accuracy and hardware cost.

View publication

Background

I grew up in Arunachal Pradesh and studied Electronics and Communication Engineering at NIT Arunachal Pradesh before joining IIT Gandhinagar for my Ph.D.

At IIT Gandhinagar, I worked with Prof. Joycee Mekie in the nanoDC Lab on in-memory computing and approximate computing. My doctoral work included circuit research, two UMC 65 nm tapeouts, and teaching IC design.

I joined Arm in Noida in October 2023 and defended my Ph.D. in June 2024. I now work on SRAM design and characterization, while continuing to write about semiconductors and mentor students.

View my CV

Arm, Noida

Senior Design Engineer, Physical IP Group.
SRAM circuit design and characterization at advanced technology nodes.

Ph.D. · IIT Gandhinagar

Electrical Engineering, nanoDC Lab.
Advisor: Prof. Joycee Mekie. Research in in-memory computing and approximate computing.

UMC 65 nm tapeouts

Worked with a student team on the design and implementation of memory and computing circuits for two chip tapeouts.

B.Tech. · NIT Arunachal Pradesh

Electronics and Communication Engineering.
Chairman Gold Medal and Institute Gold Medal.

Teaching and learning resources

During my Ph.D., I taught IC design at IIT Gandhinagar and worked as a teaching assistant for NPTEL courses in Digital Electronics and VLSI Subsystems.

I have also mentored students on circuit design and research projects. This collection includes presentations, tutorials, and course videos from my teaching and research work.

All learning resources
Breaking the memory wall for AI PresentationThe art of approximate computing PresentationVerilog and FPGA fundamentals TutorialMy semiconductor posts LinkedIn

Awards and academic service

All awards and fellowships

Research fellowships

During my Ph.D., I received the Prime Minister’s Research Fellowship and Intel India Research Fellowship in 2020. I was also an SRC Research Scholar.

Teaching award

I received IIT Gandhinagar’s Outstanding Graduate Teaching Fellow Award in 2022 for my work teaching the IC Design course.

Conference service

I served as Track Chair for ULSI Circuits, System-on-Chip, and Power SoC at ICEE 2025. I also review research papers and collaborate with students and researchers.

Collaborators

Let's connect

A good conversation
can start something.

For research discussions, invited talks, or conversations about memory design and VLSI education.

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