Improving compute and memory together
My doctoral research at IIT Gandhinagar examined how circuit and architectural choices affect the energy, performance, and robustness of domain-specific hardware, with AI workloads as a major focus.
On the compute side, I explored approximate arithmetic and number representations that reduce the cost of operations and the amount of data stored. On the memory side, I developed in-memory computing circuits and studied architectures that reduce data movement. Hardware–software codesign and modelling tools helped connect those choices with application-level behaviour.
Domain-specific hardware design with emphasis on energy efficiency, performance and robustness
Advisor: Prof. Joycee Mekie · Submitted May 2023 · Defended June 2024
IIT Gandhinagar library catalogueMy current work at Arm focuses on SRAM circuit design and characterization. The projects below describe my academic research and publicly shared work.
Compute and number representation
Arithmetic complexity and numerical precision influence the cost of computation, storage, and data transfer. These projects explore approximation and workload-appropriate representations while evaluating output quality.
Approximate posit multipliers for DNN accelerators
Co-developed a hardware–software codesign approach using approximate posit arithmetic in DNN accelerators. The work links number representation and multiplier design with compute efficiency, buffer requirements, and data-transfer cost, evaluated alongside neural-network accuracy.
View publicationApproximate adders and floating-point dividers
Worked on FPAD, a multistage approximation methodology for floating-point division, and SEDAAF, an FPGA implementation of exact and approximate adders for approximate processors. These projects explore how arithmetic design trades numerical accuracy for lower hardware cost.
Developed VosTrOF: A Unified Tool for Design Space Exploration of Approximate Arithmetic Circuits
- Designed VosTrOF, a tool that unifies four approximation strategies (Truncation, Overclocking, Voltage Overscaling, and Functional Approximation) for adders, multipliers, and dividers, enabling holistic analysis and design space exploration
- Utilized VosTrOF for eight separate image processing applications, demonstrating optimized designs
Compression and Quantization of Convolutional Neural Networks
- Surveyed compression and quantization techniques for Neural Networks to reduce memory and compute requirements during inference
- Implemented logarithmic quantization in Python for various neural networks and analyzed the effects
Memory and in-memory computing
Memory research addresses both the cost of accessing data and the opportunity to compute within the array. My work spans compute circuits, memory peripherals, architecture modelling, and compiler development.
Digital In Memory Computing (IMC) in 6T SRAM
- Conducted Compute Disturb Analysis and Proposed Mitigation techniques for SRAM 6T-based Digital IMC
- Designed IMC Architecture including Decoder and Peripherals
- Developed Compute Circuits for bit-serial addition, multiplication, and MAC operation
- Designed a Compute-enabled Sense Amplifier robust to process variation
Analog In Memory Computing in 6T SRAM
- Proposed a column-major analog IMC for multi-bit multiplication with minimal changes to peripheral circuits
- Developed a compute-disturb free IMC architecture with high dynamic range and resilience to process variations
- Identified wordline degradation as a major source of non-linearity in analog and digital IMC
- Implemented four wordline shaping techniques to improve access time and reduce inconsistency in bitline discharge
- Proposed a novel process variation tracking method for analog IMC to compensate for process variation
Simulator Design for Digital IMC
- Designed i-CACTI simulator for application-level analysis of Digital IMC
- Built FastMem simulator for accurate and fast SRAM modeling integrated with Digital IMC Compute Logic using Bit Serial and Bit Parallel paradigms of computation
- Built NeuroCACTI-IMC to calculate performance metrics for in-memory computations in SRAM-based memory sub-system, achieving 8X improvement in EDP for BPA and BSA by modifying memory array structure.
Developed SRAM Memory Compiler
- Analyzed the performance metrics of SRAM arrays generated by OpenRAM compiler in NCSU45nm, ranging from 8B to 4KB
- Ported OpenRAM memory compiler to UMC65nm and UMC28nm at both schematic and layout levels, performing a detailed analysis across multiple technologies
- Optimized the performance of the complete Memory subsystem by properly sizing transistors in custom library cells and implementing circuit-level changes
Heterogeneous SRAM Cell Sizing for Low-Power Image Processing Applications
- Designed an 8x8 array of 6T SRAM cells with 8 cells in a row of heterogeneous/different sizes
- Simulated and performed read/write operations with the help of peripheral circuitry in Cadence Virtuoso using UMC 65nm technology
- Developed a 1000X faster algorithm than the proposed one to find optimum sizes for heterogeneous SRAM cells using the Dynamic Programming approach.
Design tools and other projects
Related projects in circuit optimisation, EDA automation, and machine learning.
Automatic Analog Circuit Design Tool using Machine Learning
- Utilized machine learning to model technology parameters for automatic analog circuit design
- Created a design space of circuits (Common Source and Two Stage Operational Amplifier) using the machine learning model
- Employed Bayesian optimization to find the optimum design within the design space
- Implemented an active learning plugin for dataset generation when it was not readily available
Xilinx Vivado Automation Using Python
- Automated Xilinx Vivado's Synthesis and Simulation flow using Python, Bash, and Tcl
- Designed a wrapper to simulate and synthesize a large number of RTL files, providing metrics in a single file
A Deep Learning based Automatic Image Colorization Framework
- Used Deep Learning to colorize grayscale images
- Utilized class-rebalancing at training time to enhance the diversity of colors in the output image
- Implemented the system as a feed-forward net in a Convolutional Neural Network at test time, trained on the Imagenet Dataset